This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-374734, filed Dec. 7, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to, for example, a voltage generator circuit. More specifically, the present invention relates to a voltage generator circuit for use in a semiconductor device such as a semiconductor memory or the like.
2. Description of the Related Art
A semiconductor device such as a semiconductor memory device or the like has a voltage generator circuit which supplies a predetermined potential to generate a bias and the like necessary for its operations. The voltage generator circuit is constructed, for example, by using transistors, resistor elements, and the like. A constant potential should desirably be supplied, independently from changes in load currents.
FIG. 10 shows an example of a conventional voltage generator circuit 22 used in a semiconductor device. This kind of voltage generator circuit is described in Japanese Patent Application No. 2001-133460. As shown in FIG. 10, a P-type MOS (Metal Oxide Semiconductor) TP21 and an N-type MOS transistor TN21 connected in series are provided between a feed end of a power-source voltage and an output end of a voltage. Similarly, MOS transistors TP22 and TN22 connected in series are provided between the supplying end of a power-source potential and the output end of a voltage. The gate of the MOS transistor TP21 is supplied with a NOT (or inverted) logic signal (hereinafter the xe2x80x9cNOT logicxe2x80x9d will be referred to merely by xe2x80x9c/xe2x80x9d) of a signal xe2x80x9cstandbyxe2x80x9d which corresponds to a standby period of a semiconductor memory, from a control circuit not shown. The gate of the MOS transistor TP22 is supplied with a signal xe2x80x9c/activexe2x80x9d which corresponds to an active period of a semiconductor memory. Reference symbol I21 denotes a load current.
The MOS transistors TN21 and TN22 have gate widths different from each other. As shown in FIG. 11, the gate widths are designed such that the voltage generator circuit 22 outputs a voltage of about 2.5 V, using the MOS transistor TN 21 when the lord current I21 is 100 nA, and using the MOS transistor TN 22 when the lord current I21 is 1 mA.
The operation of the voltage generator circuit 22 thus constructed will now be explained schematically. As shown in FIG. 12, while the semiconductor memory is in a standby state, the MOS transistor TN21 shown in FIG. 10 turns on. At this time, the load current 121 is about 0.1 xcexcA. While the semiconductor memory performs a sensing operation, the MOS transistor TN22 shown in FIG. 10 turns on. The sensing period is given to read, by means of a sense amplifier, the electric charge which has moved from a memory cell to a bit line. A greater current is therefore consumed to drive the sense amplifier. During the sensing period, the load current I21 is, for example, 1 mA.
During a restoring period, the semiconductor memory writes back data retained by the sense amplifier into a memory cell. The load current is about 0.1 to 10 xcexcA in the restoring period. Then, the semiconductor memory shifts to a standby state, and the MOS transistor TN21 turns on again. In series of the mentioned operations, the output voltage of the voltage generator circuit is maintained substantially at 2.5 V, as shown in FIG. 11.
As described above, the output voltage is kept constant by controlling the MOS transistors TN21 and TN22 in accordance with the state of the semiconductor memory.
Meanwhile, several semiconductor memories further cover a holding operation in addition to the sensing and restoring operations, during the active period. During the holding period, the sense amplifier does not write back but holds the read data. The holding period is very short in normal accessing methods. In several accessing methods, however, the holding period is long. An example of such a long holding period will be a case that a long time is required until a writing operation starts after the operation of the sense amplifier because the memory device is operated at a cycle time slower than a fastest cycle time. In addition, the holding period is long if the memory device is operated in a page mode.
FIG. 13 shows a load current and an output voltage when a conventional voltage generator circuit is used in a semiconductor memory having a long holding period. As shown in FIG. 13, the voltage generator circuit drives the MOS transistor TN22 through sensing, holding, and restoring periods. The output voltage, however, increases because the load current I21 is as low as about 10 xcexcA during the holding period. If the restoring period is started in a state that the output voltage is high, the voltage applied to the memory cell increases. The reliability of the memory cell therefore deteriorates, e.g., capacitors of memory cells are degraded.
According to a first aspect of the present invention, there is provided a voltage generator circuit which generates a voltage supplied to an internal circuit, and comprises: a power source terminal supplied with a power source voltage; first, second, and third switching elements each having first and second terminals, the first terminal of each of the switching elements being connected to the power source terminal; a first transistor having a first driving capability and a current path which has first and second ends, the first end being connected to the second terminal of the first switching element; a second transistor having a second driving capability, which is different from the first driving capability, and a current path which has first and second ends, the first end being connected to the second terminal of the second switching element; a third transistor having a third driving capability, which is different from the first and second driving capabilities, and a current path having first and second ends, the first end being connected to the second terminal of the third switching element; and an output terminal which outputs the voltage supplied to the internal circuit and is connected to the second end of each of the current paths of the first, second, and third transistors.